When a digital signal is transmitted across a data bus using two levels, i.e., binary signaling, the signal switches between two values, representing a binary 0 or 1, respectively. For example, the voltage on a conductor, such as a wire or a printed wiring board trace, may be driven to a first value to signify a binary 0 and to a second value to signify a binary 1.
Data may be sent across a bus at a higher data throughput, for a given clock rate, using multi-level signaling. For example, in four-level signaling, which may be referred to as four-level pulse amplitude modulation (PAM-4), the voltage on conductor may take one of four values. In a PAM-4 receiver the received signal may then be converted, for each of the four voltage values, to a pair of bits, with a first value corresponding to binary 00, a second value corresponding to binary 01, a third value corresponding to binary 10, and a fourth value corresponding to binary 11, respectively. In other embodiments the correspondence between the voltage levels and pairs of bits may be different, or another parallel signaling scheme, such as one-hot encoding, or inverse one-hot encoding, may be used.
A multi-level receiver, which receives a multi-level signal as input and produces parallel binary signals as output, may be constructed with multiple comparators in parallel, which may be identical except for the threshold voltage to which each is connected. One input of each comparator may be connected to the received signal Vin, and the other input may be connected to a threshold voltage.
Each comparator in such a multi-level receiver may be composed of a differential pair of transistors, with each transistor being connected to a resistor and to a shared current source. The current flowing through one of the resistors and one of the transistors in such a differential pair, and through the current source, dissipates power, and if there are several such comparators in a receiver then several times as much power is dissipated. Power consumption may be reduced by operating the comparators in a sequential comparison mode in which only one comparator is active at any given time, but this approach, while reducing power consumption, also reduces the speed at which the receiver is capable of operating, resulting in slower data transmission and, accordingly, a loss of at least some of the benefits of using multi-level signaling.
Thus, there is a need for a low-power, high-speed system and method for receiving a signal employing multi-level signaling.